This invention relates to integrated circuit arrays of single capacitor, single MOS transistor memory cells, and more particularly to an improved method of fabricating such cells.
Conventional processes for fabricating MOS memories using a single capacitor and a single MOS transistor utilize several photolithographic masking steps that require strict alignment tolerances, thereby greatly reducing the effective area of the cell and limiting the achievable cell density. Accordingly, there is a strong need for a process that greatly reduces the number of masking steps where alignment is critical.